Hold-off timing synchronization

You can configure hold-off time for Synchronous Ethernet interfaces and external clock synchronization sources to prevent rapid successive switching. If an interface goes down, hold-off time delays short signal failures from being sent to the clock selection process. If you configure hold-off time when quality level (QL) mode is enabled, the configured quality level is used in the clock selection process during the hold-off time period. After the hold-off time period ends, a signal failure is sent to the clock selection process. To configure hold-off time, include the hold-off-time statement at the [set chassis synchronization source interfaces (external-a | external-b | interface interface-name)] hierarchy level.